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CY2305 CY2309
Low-Cost 3.3V Zero Delay Buffer
Features
* 10-MHz to 100-/133-MHz operating range, compatible with CPU and PCI bus frequencies * Zero input-output propagation delay * Multiple low-skew outputs -- Output-output skew less than 250 ps -- Device-device skew less than 700 ps -- One input drives five outputs (CY2305) -- One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309) * Less than 200 ps cycle-cycle jitter is compatible with Pentium based systems * Test Mode to bypass PLL (CY2309 only, see Select Input Decoding table on page 2) * Available in space-saving 16-pin, 150-mil SOIC or 4.4mm TSSOP packages (CY2309), and 8-pin, 150-mil SOIC package (CY2305) * 3.3V operation, advanced 0.65 CMOS technology * Industrial Temperature available up to 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY2309 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding table on page 2. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY2305 and CY2309 PLLs enter a Power-Down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 12.0 A of current draw for commercial temperature devices and 25.0 A for industrial temperature parts. The CY2309 PLL shuts down in one additional case as shown in the table below. Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. All outputs have less than 200 ps of cycle-cycle jitter. The input to output propagation delay on both devices is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. The CY2305/CY2309 is available in two/three different configurations, as shown in the ordering information (page 10). The CY2305-1/CY2309-1 is the base part. The CY2305-1H/ CY2309-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1's.
Functional Description
The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions of each device operate at
Block Diagram
PLL
REF CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 Select Input Decoding S1
2309-1
Pin Configuration
SOIC/TSSOP Top View
MUX REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
2309-2
S2
CLKB2 CLKB3 CLKB4 REF CLK2 CLK1 GND
1 2 3 4
SOIC Top View
8 7 6 5
CLKOUT CLK4 V DD CLK3
2309-3
Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 December 16, 1999
CY2305 CY2309
Select Input Decoding for CY2309
S2 0 0 1 1 S1 0 1 0 1 CLOCK A1-A4 Three-State Driven Driven Driven CLOCK B1-B4 Three-State Three-State Driven Driven CLKOUT[1] Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown N N Y N
Note: 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB pins
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load, equal to that on
other outputs, for obtaining zero input-output delay. If input to output delay adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note "CY2305 and CY2309 as PCI and SDRAM Buffers."
2
CY2305 CY2309
Pin Description for CY2309
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF
[2] [3]
Signal CLKA1 VDD GND CLKB1 S2 S1
[4] [4] [3] [3]
Description Input reference frequency, 5V-tolerant input Buffered clock output, Bank A Buffered clock output, Bank A 3.3V supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Select input, bit 2 Select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Ground 3.3V supply
CLKA2[3]
CLKB2[3]
CLKB3 GND VDD CLKA3
CLKB4[3]
[3]
Buffered clock output, Bank A Buffered clock output, Bank A Buffered output, internal feedback on this pin
CLKA4[3] CLKOUT
[3]
Pin Description for CY2305
Pin 1 2 3 4 5 6 7 8 REF
[2]
Signal CLK2[3] CLK1 GND CLK3 VDD CLK4
[3] [3] [3] [3]
Description Input reference frequency, 5V-tolerant input Buffered clock output Buffered clock output Ground Buffered clock output 3.3V supply Buffered clock output Buffered clock output, internal feedback on this pin
CLKOUT
Notes: 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-ups on these inputs.
Maximum Ratings
Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Input Voltage (Except REF) ............-0.5V to VDD + 0.5V DC Input Voltage REF ............................................. -0.5V to 7V
Storage Temperature ................................. -65C to +150C Max. Soldering Temperature (10 sec.) ....................... 260C Junction Temperature ................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................ >2,000V
3
CY2305 CY2309
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Description Min. 3.0 0 Max. 3.6 70 30 10 7 Unit V C pF pF pF
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage
[5] [5]
Test Conditions
Min. 2.0
Max. 0.8
Unit V V A A V V
Input HIGH Voltage Input LOW Current Input HIGH Current
VIN = 0V VIN = V DD IOL = 8 mA (-1) IOH = 12 mA (-1H) IOH = -8 mA (-1) IOL = -12 mA (-1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VDD 2.4
50.0 100.0 0.4
Output LOW Voltage[6] Output HIGH Voltage[6] Power Down Supply Current Supply Current
12.0 32.0
A mA
Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices[7]
Parameter t1 Name Output Frequency Duty Cycle[6] = t2 / t1 t3 t4 t5 t6 t7 tJ tLOCK Rise Time[6] Fall Time
[6]
Test Conditions 30-pF load 10-pF load Measured at 1.4V, Fout = 66.67 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded
Min. 10 10 40.0
Typ.
Max. 100 133.33
Unit MHz MHz % ns ns ps ps ps ps ms
50.0
60.0 2.50 2.50 250
Output to Output Skew[6]
Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[6] Device to Device Skew [6] Cycle to Cycle Jitter[6] PLL Lock Time[6] Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin
0 0
350 700 200 1.0
Notes: 5. REF input has a threshold voltage of VDD/2. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. 7. All parameters specified with loaded outputs.
4
CY2305 CY2309
Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices[7]
Parameter t1 Name Output Frequency Duty Cycle[6] = t2 / t1 Duty Cycle t3 t4 t5 t6 t7 t8 tJ tLOCK Rise Time
[6]
Description 30-pF load 10-pF load Measured at 1.4V, Fout = 66.67 MHz Measured at 1.4V, Fout <50.0 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V
[6]
Min. 10 10 40.0 45.0
Typ.
Max. 100 133.33
Unit MHz MHz % % ns ns ps ps ps V/ns
50.0 50.0
60.0 55.0 1.50 1.50 250
= t2 / t1
[6]
Fall Time[6] Output to Output Skew
All outputs equally loaded 0 0 1
Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[6] Device to Device Skew [6] Output Slew Rate[6] Cycle to Cycle Jitter[6] PLL Lock Time[6] Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin
350 700
200 1.0
ps ms
Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Description Min. 3.0 -40 Max. 3.6 85 30 10 7 Unit V
C
pF pF pF
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage[5] Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[6] Output HIGH Voltage[6] Power Down Supply Current Supply Current
[5]
Test Conditions
Min. 2.0
Max. 0.8
Unit V V A A V V
VIN = 0V VIN = V DD IOL = 8 mA (-1) IOH =12 mA (-1H) IOH = -8 mA (-1) IOL = -12 mA (-1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VDD 2.4
50.0 100.0 0.4
25.0 35.0
A mA
5
CY2305 CY2309
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices[7]
Parameter t1 Name Output Frequency Duty Cycle[6] = t2 / t1 t3 t4 t5 t6 t7 tJ tLOCK Rise Time
[6]
Test Conditions 30-pF load 10-pF load Measured at 1.4V, Fout = 66.67 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V
[6]
Min. 10 10 40.0
Typ.
Max. 100 133.33
Unit MHz MHz % ns ns ps ps ps ps ms
50.0
60.0 2.50 2.50 250
Fall Time[6] Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge[6] Device to Device Skew[6] Cycle to Cycle Jitter[6] PLL Lock Time[6]
All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin 0 0
350 700 200 1.0
Switching Characteristics for CY2305SC-1H and CY2309SC-1H Industrial Temperature Devices[7]
Parameter t1 Name Output Frequency Duty Cycle[6] = t2 / t1 Duty Cycle t3 t4 t5 t6 t7 t8 tJ tLOCK Rise Time
[6]
Description 30-pF load 10-pF load Measured at 1.4V, Fout = 66.67 MHz Measured at 1.4V, Fout < 50.0 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V
[6]
Min. 10 10 40.0 45.0
Typ.
Max. 100 133.33
Unit MHz MHz % % ns ns ps ps ps V/ns
50.0 50.0
60.0 55.0 1.50 1.50 250
= t2 / t1
[6]
Fall Time[6] Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge[6] Device to Device Skew[6] Output Slew Rate[6] Cycle to Cycle Jitter[6] PLL Lock Time[6]
All outputs equally loaded Measured at V DD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin 1 0 0
350 700
200 1.0
ps ms
Switching Waveforms
Duty Cycle Timing
t1 t2 1.4V 1.4V 1.4V
2309-4
6
CY2305 CY2309
Switching Waveforms (continued)
All Outputs Rise/Fall Time
2.0V 0.8V t3 2.0V 0.8V t4
2309-5
3.3V 0V
OUTPUT
Output-Output Skew
OUTPUT
1.4V
OUTPUT t5
1.4V
2309-6
Input-Output Propagation Delay
INPUT
VDD /2
OUTPUT t6
VDD/2
2309-7
Device-Device Skew
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2 t7
VDD /2
2309-8
7
CY2305 CY2309
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1 and CY2309-1
Duty Cycle Vs VD D (for 30 pF Loads over Frequency - 3.3V, 25C)
60 58 56
Duty C ycle (% )
Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C)
60 58 56 54
Duty Cycle (%) 33 MHz 66 MHz 100 MHz
54 52 50 48 46 44 42 40 3 3.1 3.2 3.3
VDD (V)
52 50 48 46 44 42 40
33 MHz 66 MHz 100 MHz 133 MHz
3.4
3.5
3.6
3
3.1
3.2
3.3
VDD (V)
3.4
3.5
3.6
D uty C ycle Vs Frequency (for 30 pF Loads ov er T emperature - 3.3V)
60 58 56 54
Duty Cycle (%)
D uty C ycle Vs Fre quency (for 15 pF Loads over T emperature - 3.3V)
60 58 56 -40C 0C 25C 70C 85C
Duty Cycle (%)
54 52 50 48 46 44 42 40
-40C 0C 25C 70C 85C
52 50 48 46 44 42 40 20 40 60 80
Fre que ncy (MHz)
100
120
140
20
40
60
80
Fre quency (M Hz )
100
120
140
IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C)
140 120 100 IDD (mA) 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs 33 MHz 66 MHz 100 MHz IDD (mA) 140 120 100 80 60 40 20 0 0 1
IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C)
33 MHz 66 MHz 100 MHz
2
3
4
5
6
7
8
9
# of Loaded Outputs
Notes: 8. Duty Cycle is taken from typical chip measured at 1.4V. 9. I DD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = frequency (Hz))
8
CY2305 CY2309
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1H and CY2309-1H
Duty Cycle Vs VD D (for 30 pF Loads over Frequency - 3.3 V, 25 C)
60 58 56
Duty Cycle (% )
Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C)
60 58 56 54 Duty Cycle (%) 33 MHz 66 MHz 100 MHz 52 50 48 46 44 42 40 33 MHz 66 MHz 100 MHz 133 MHz
54 52 50 48 46 44 42 40 3 3.1 3.2 3.3
VDD (V)
3.4
3.5
3.6
3
3.1
3.2
3.3 VDD (V)
3.4
3.5
3.6
Duty Cycle Vs Fre quency (for 30 pF Loads ove r T empe rature - 3.3V)
Duty Cycle Vs Frequency (for 15 pF Loads ove r T emperature - 3.3V)
60 58 56 -40C 0C 25C 70C 85C
Duty Cycle (%)
60 58 56 54
Duty Cycle (%)
54 52 50 48 46 44 42 40
-40C 0C 25C 70C 85C
52 50 48 46 44 42 40 20 40 60 80
Fre que ncy (MHz)
100
120
140
20
40
60
80
Freque ncy (MHz)
100
120
140
IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C)
160 140 120 IDD (mA) 33 MHz 66 MHz 100 MHz IDD (mA) 100 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs 160 140 120 100 80 60 40 20 0 0 1
IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C)
33 MHz 66 MHz 100 MHz
2
3
4
5
6
7
8
9
# of Loaded Outputs
9
CY2305 CY2309
Test Circuits Test Circuit # 1 VDD 0.1 F CLK out
OUTPUTS
Test Circuit # 2 VDD 0.1 F
OUTPUTS 1 k
CLOAD VDD 0.1 F
GND GND
10 pF VDD 0.1 F
GND GND 1 k
For parameter t8 (output slew rate) on -1H devices
Ordering Information
Ordering Code CY2305SC-1 CY2305SI-1 CY2305SC-1H CY2305SI-1H CY2309SC-1 CY2309SI-1 CY2309SC-1H CY2309SI-1H CY2309ZC-1H CY2309ZI-1H Document #: 38-00530-F Package Name S8 S8 S8 S8 S16 S16 S16 S16 Z16 Z16 Package Type 8-pin 150-mil SOIC 8-pin 150-mil SOIC 8-pin 150-mil SOIC 8-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
10
CY2305 CY2309
Package Diagrams
8-Lead (150-Mil) SOIC S8
51-85066-A
16-Lead (150-Mil) Molded SOIC S16
51-85068-A
11
CY2305 CY2309
Package Diagrams (continued)
16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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